Basic_Frame_TypeC_2023_Omni
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bmi088_reg.h
1#ifndef BMI088REG_H
2#define BMI088REG_H
3
4#define BMI088_ACC_CHIP_ID 0x00 // the register is " Who am I "
5#define BMI088_ACC_CHIP_ID_VALUE 0x1E
6
7#define BMI088_ACC_ERR_REG 0x02
8#define BMI088_ACCEL_CONGIF_ERROR_SHFITS 0x2
9#define BMI088_ACCEL_CONGIF_ERROR (1 << BMI088_ACCEL_CONGIF_ERROR_SHFITS)
10#define BMI088_FATAL_ERROR_SHFITS 0x0
11#define BMI088_FATAL_ERROR (1 << BMI088_FATAL_ERROR)
12
13#define BMI088_ACC_STATUS 0x03
14#define BMI088_ACCEL_DRDY_SHFITS 0x7
15#define BMI088_ACCEL_DRDY (1 << BMI088_ACCEL_DRDY_SHFITS)
16
17#define BMI088_ACCEL_XOUT_L 0x12
18#define BMI088_ACCEL_XOUT_M 0x13
19#define BMI088_ACCEL_YOUT_L 0x14
20#define BMI088_ACCEL_YOUT_M 0x15
21#define BMI088_ACCEL_ZOUT_L 0x16
22#define BMI088_ACCEL_ZOUT_M 0x17
23
24#define BMI088_SENSORTIME_DATA_L 0x18
25#define BMI088_SENSORTIME_DATA_M 0x19
26#define BMI088_SENSORTIME_DATA_H 0x1A
27
28#define BMI088_ACC_INT_STAT_1 0x1D
29#define BMI088_ACCEL_DRDY_INTERRUPT_SHFITS 0x7
30#define BMI088_ACCEL_DRDY_INTERRUPT (1 << BMI088_ACCEL_DRDY_INTERRUPT_SHFITS)
31
32#define BMI088_TEMP_M 0x22
33
34#define BMI088_TEMP_L 0x23
35
36#define BMI088_ACC_CONF 0x40
37#define BMI088_ACC_CONF_MUST_Set 0x80
38#define BMI088_ACC_BWP_SHFITS 0x4
39#define BMI088_ACC_OSR4 (0x0 << BMI088_ACC_BWP_SHFITS)
40#define BMI088_ACC_OSR2 (0x1 << BMI088_ACC_BWP_SHFITS)
41#define BMI088_ACC_NORMAL (0x2 << BMI088_ACC_BWP_SHFITS)
42
43#define BMI088_ACC_ODR_SHFITS 0x0
44#define BMI088_ACC_12_5_HZ (0x5 << BMI088_ACC_ODR_SHFITS)
45#define BMI088_ACC_25_HZ (0x6 << BMI088_ACC_ODR_SHFITS)
46#define BMI088_ACC_50_HZ (0x7 << BMI088_ACC_ODR_SHFITS)
47#define BMI088_ACC_100_HZ (0x8 << BMI088_ACC_ODR_SHFITS)
48#define BMI088_ACC_200_HZ (0x9 << BMI088_ACC_ODR_SHFITS)
49#define BMI088_ACC_400_HZ (0xA << BMI088_ACC_ODR_SHFITS)
50#define BMI088_ACC_800_HZ (0xB << BMI088_ACC_ODR_SHFITS)
51#define BMI088_ACC_1600_HZ (0xC << BMI088_ACC_ODR_SHFITS)
52
53#define BMI088_ACC_RANGE 0x41
54
55#define BMI088_ACC_RANGE_SHFITS 0x0
56#define BMI088_ACC_RANGE_3G (0x0 << BMI088_ACC_RANGE_SHFITS)
57#define BMI088_ACC_RANGE_6G (0x1 << BMI088_ACC_RANGE_SHFITS)
58#define BMI088_ACC_RANGE_12G (0x2 << BMI088_ACC_RANGE_SHFITS)
59#define BMI088_ACC_RANGE_24G (0x3 << BMI088_ACC_RANGE_SHFITS)
60
61#define BMI088_INT1_IO_CTRL 0x53
62#define BMI088_ACC_INT1_IO_ENABLE_SHFITS 0x3
63#define BMI088_ACC_INT1_IO_ENABLE (0x1 << BMI088_ACC_INT1_IO_ENABLE_SHFITS)
64#define BMI088_ACC_INT1_GPIO_MODE_SHFITS 0x2
65#define BMI088_ACC_INT1_GPIO_PP (0x0 << BMI088_ACC_INT1_GPIO_MODE_SHFITS)
66#define BMI088_ACC_INT1_GPIO_OD (0x1 << BMI088_ACC_INT1_GPIO_MODE_SHFITS)
67#define BMI088_ACC_INT1_GPIO_LVL_SHFITS 0x1
68#define BMI088_ACC_INT1_GPIO_LOW (0x0 << BMI088_ACC_INT1_GPIO_LVL_SHFITS)
69#define BMI088_ACC_INT1_GPIO_HIGH (0x1 << BMI088_ACC_INT1_GPIO_LVL_SHFITS)
70
71#define BMI088_INT2_IO_CTRL 0x54
72#define BMI088_ACC_INT2_IO_ENABLE_SHFITS 0x3
73#define BMI088_ACC_INT2_IO_ENABLE (0x1 << BMI088_ACC_INT2_IO_ENABLE_SHFITS)
74#define BMI088_ACC_INT2_GPIO_MODE_SHFITS 0x2
75#define BMI088_ACC_INT2_GPIO_PP (0x0 << BMI088_ACC_INT2_GPIO_MODE_SHFITS)
76#define BMI088_ACC_INT2_GPIO_OD (0x1 << BMI088_ACC_INT2_GPIO_MODE_SHFITS)
77#define BMI088_ACC_INT2_GPIO_LVL_SHFITS 0x1
78#define BMI088_ACC_INT2_GPIO_LOW (0x0 << BMI088_ACC_INT2_GPIO_LVL_SHFITS)
79#define BMI088_ACC_INT2_GPIO_HIGH (0x1 << BMI088_ACC_INT2_GPIO_LVL_SHFITS)
80
81#define BMI088_INT_MAP_DATA 0x58
82#define BMI088_ACC_INT2_DRDY_INTERRUPT_SHFITS 0x6
83#define BMI088_ACC_INT2_DRDY_INTERRUPT (0x1 << BMI088_ACC_INT2_DRDY_INTERRUPT_SHFITS)
84#define BMI088_ACC_INT1_DRDY_INTERRUPT_SHFITS 0x2
85#define BMI088_ACC_INT1_DRDY_INTERRUPT (0x1 << BMI088_ACC_INT1_DRDY_INTERRUPT_SHFITS)
86
87#define BMI088_ACC_SELF_TEST 0x6D
88#define BMI088_ACC_SELF_TEST_OFF 0x00
89#define BMI088_ACC_SELF_TEST_POSITIVE_SIGNAL 0x0D
90#define BMI088_ACC_SELF_TEST_NEGATIVE_SIGNAL 0x09
91
92#define BMI088_ACC_PWR_CONF 0x7C
93#define BMI088_ACC_PWR_SUSPEND_MODE 0x03
94#define BMI088_ACC_PWR_ACTIVE_MODE 0x00
95
96#define BMI088_ACC_PWR_CTRL 0x7D
97#define BMI088_ACC_ENABLE_ACC_OFF 0x00
98#define BMI088_ACC_ENABLE_ACC_ON 0x04
99
100#define BMI088_ACC_SOFTRESET 0x7E
101#define BMI088_ACC_SOFTRESET_VALUE 0xB6
102
103#define BMI088_GYRO_CHIP_ID 0x00
104#define BMI088_GYRO_CHIP_ID_VALUE 0x0F
105
106#define BMI088_GYRO_X_L 0x02
107#define BMI088_GYRO_X_H 0x03
108#define BMI088_GYRO_Y_L 0x04
109#define BMI088_GYRO_Y_H 0x05
110#define BMI088_GYRO_Z_L 0x06
111#define BMI088_GYRO_Z_H 0x07
112
113#define BMI088_GYRO_INT_STAT_1 0x0A
114#define BMI088_GYRO_DYDR_SHFITS 0x7
115#define BMI088_GYRO_DYDR (0x1 << BMI088_GYRO_DYDR_SHFITS)
116
117#define BMI088_GYRO_RANGE 0x0F
118#define BMI088_GYRO_RANGE_SHFITS 0x0
119#define BMI088_GYRO_2000 (0x0 << BMI088_GYRO_RANGE_SHFITS)
120#define BMI088_GYRO_1000 (0x1 << BMI088_GYRO_RANGE_SHFITS)
121#define BMI088_GYRO_500 (0x2 << BMI088_GYRO_RANGE_SHFITS)
122#define BMI088_GYRO_250 (0x3 << BMI088_GYRO_RANGE_SHFITS)
123#define BMI088_GYRO_125 (0x4 << BMI088_GYRO_RANGE_SHFITS)
124
125#define BMI088_GYRO_BANDWIDTH 0x10
126// the first num means Output data rate, the second num means bandwidth
127#define BMI088_GYRO_BANDWIDTH_MUST_Set 0x80
128#define BMI088_GYRO_2000_532_HZ 0x00
129#define BMI088_GYRO_2000_230_HZ 0x01
130#define BMI088_GYRO_1000_116_HZ 0x02
131#define BMI088_GYRO_400_47_HZ 0x03
132#define BMI088_GYRO_200_23_HZ 0x04
133#define BMI088_GYRO_100_12_HZ 0x05
134#define BMI088_GYRO_200_64_HZ 0x06
135#define BMI088_GYRO_100_32_HZ 0x07
136
137#define BMI088_GYRO_LPM1 0x11
138#define BMI088_GYRO_NORMAL_MODE 0x00
139#define BMI088_GYRO_SUSPEND_MODE 0x80
140#define BMI088_GYRO_DEEP_SUSPEND_MODE 0x20
141
142#define BMI088_GYRO_SOFTRESET 0x14
143#define BMI088_GYRO_SOFTRESET_VALUE 0xB6
144
145#define BMI088_GYRO_CTRL 0x15
146#define BMI088_DRDY_OFF 0x00
147#define BMI088_DRDY_ON 0x80
148
149#define BMI088_GYRO_INT3_INT4_IO_CONF 0x16
150#define BMI088_GYRO_INT4_GPIO_MODE_SHFITS 0x3
151#define BMI088_GYRO_INT4_GPIO_PP (0x0 << BMI088_GYRO_INT4_GPIO_MODE_SHFITS)
152#define BMI088_GYRO_INT4_GPIO_OD (0x1 << BMI088_GYRO_INT4_GPIO_MODE_SHFITS)
153#define BMI088_GYRO_INT4_GPIO_LVL_SHFITS 0x2
154#define BMI088_GYRO_INT4_GPIO_LOW (0x0 << BMI088_GYRO_INT4_GPIO_LVL_SHFITS)
155#define BMI088_GYRO_INT4_GPIO_HIGH (0x1 << BMI088_GYRO_INT4_GPIO_LVL_SHFITS)
156#define BMI088_GYRO_INT3_GPIO_MODE_SHFITS 0x1
157#define BMI088_GYRO_INT3_GPIO_PP (0x0 << BMI088_GYRO_INT3_GPIO_MODE_SHFITS)
158#define BMI088_GYRO_INT3_GPIO_OD (0x1 << BMI088_GYRO_INT3_GPIO_MODE_SHFITS)
159#define BMI088_GYRO_INT3_GPIO_LVL_SHFITS 0x0
160#define BMI088_GYRO_INT3_GPIO_LOW (0x0 << BMI088_GYRO_INT3_GPIO_LVL_SHFITS)
161#define BMI088_GYRO_INT3_GPIO_HIGH (0x1 << BMI088_GYRO_INT3_GPIO_LVL_SHFITS)
162
163#define BMI088_GYRO_INT3_INT4_IO_MAP 0x18
164
165#define BMI088_GYRO_DRDY_IO_OFF 0x00
166#define BMI088_GYRO_DRDY_IO_INT3 0x01
167#define BMI088_GYRO_DRDY_IO_INT4 0x80
168#define BMI088_GYRO_DRDY_IO_BOTH (BMI088_GYRO_DRDY_IO_INT3 | BMI088_GYRO_DRDY_IO_INT4)
169
170#define BMI088_GYRO_SELF_TEST 0x3C
171#define BMI088_GYRO_RATE_OK_SHFITS 0x4
172#define BMI088_GYRO_RATE_OK (0x1 << BMI088_GYRO_RATE_OK_SHFITS)
173#define BMI088_GYRO_BIST_FAIL_SHFITS 0x2
174#define BMI088_GYRO_BIST_FAIL (0x1 << BMI088_GYRO_BIST_FAIL_SHFITS)
175#define BMI088_GYRO_BIST_RDY_SHFITS 0x1
176#define BMI088_GYRO_BIST_RDY (0x1 << BMI088_GYRO_BIST_RDY_SHFITS)
177#define BMI088_GYRO_TRIG_BIST_SHFITS 0x0
178#define BMI088_GYRO_TRIG_BIST (0x1 << BMI088_GYRO_TRIG_BIST_SHFITS)
179
180#endif